1. Field of the Invention
The present invention relates to delay line calibration mechanisms, and more particularly to a delay line calibration mechanism with simplified circuit architecture and related multi-clock signal generator.
2. Description of the Prior Art
Delay lines are often utilized in various electronics applications for generating a precise delay. Delay-locked loops (DLLs) and delay lines with calibration are two primary implementations. To calibrate a delay line, a replica delay line is utilized. A phase detector compares phase of the output of the replica delay line with phase of a reference clock, and a delay control circuit controls the delay amount of the replica delay line based on the phase difference detected by the phase detector. When the output of the replica delay line and the reference clock are phase-matched, the calibration amount is determined. In this mechanism, it is assumed that the calibrated delay line and the replica delay line are ideally identical, however, there is mismatch between them, and a large amount of jitter is generated accordingly. In addition, the replica delay line increases circuit area and power consumption.
Delay lines are formed of logic circuits which may comprise both active and passive elements that provide delay of the clock inputted to the delay line. However, the amount of delay provided by each circuit element may vary under changing environmental conditions, including temperature, supply voltage, process, and age. As delay lines are called upon to provide precise delay, variation of the amount of delay has potential to wreak havoc in electronic systems. Thus, it is desirable that the delay lines be self-calibrating in order to adjust to the environment, and operate normally throughout their lifetime. Further, it is desirable that the delay lines be able to perform self-calibration during operation, without having to take the electronic system offline for calibration of the delay lines.